A non-volatile memory cell is known to comprise a MOS transistor having a first terminal or floating gate terminal with a high DC impedance and a second terminal or control gate terminal driven by means of control voltages.
By applying suitable voltage values to the cell terminals, the amount of the charge present in the floating gate can be varied and the transistor can be brought to either of two logic states. Thus, the transistor can function as a logic memory element.
As is known, today's electronic memory circuits contain thousands of cells arranged in matrix form and integrated to a semiconductor at very high packing rates.
In circuits of this type, different circuit portions are respectively arranged to perform cell programming, erasing, and reading operations.
For instance, to read the memory cells, a dedicated circuit is normally used which is connected to a so-called "virgin" cell, i.e., a reference cell which has never undergone memory cycles.
In addition to the reference cell, the read circuit comprises a specially responsive differential amplifier, known as the sense amplifier, which includes a two-input comparator. A first input of the comparator is connected to a circuit leg including a cell to be read, whereas the other input is connected to a second leg including the reference cell. The voltage value obtained at the comparator output will correspond to the logic state of the cell.
Cell reading is based, therefore, on an unbalanced condition of the comparator due to the different currents present in the leg of the cell to be read and the leg of the reference cell.
The circuit portion dedicated to cell reading may also be used to perform testing operations which allow the proper operation of the cell matrix to be checked.
Specifically, during a testing step, it is important that the distribution of the threshold voltages V.sub.T among the cells forming the memory matrix can be checked.
It is a current practice to perform this check by obtaining the distribution for the number of cells which, at a given gate voltage Vgate, would cause the sense amplifier to change over.
The test is carried out by adjusting the gate voltage Vgate of the cell matrix. This voltage is provided during this test through an external terminal (pin) other than the supply voltage Vdd terminal. In a memory circuit, that terminal may be the terminal intended to receive the programming voltage Vpp, when applied an appropriate voltage value.
Thereafter, the reference cell is connected to the reference leg and a current Iref flows through the reference cell leg associated with the sense amplifier.
Finally, the value of the voltage being applied to the external terminal is varied, and the current values which appear at the matrix output are sequentially noted, which values will indicate the threshold voltage distribution. Measuring the threshold voltage of a selected memory cell is well-known in the art and are described in detail in U.S. Pat. Nos. 4,253,059 (1981) and 4,301,535 (1981), both of which are incorporated herein by reference.
This invention is related to this specific field of application, and is directed to further improve and facilitate the measurement of this threshold voltage distribution.